Search - vhdl ram

[Other resource] 一些VHDL源代码

Description: 内有波形发生器，加法器，经典双进程状态机，伪随机熟产生器，相应加法器的测试向量，16×8bit RAM,FIFO,通用RAM等源程序-within waveform generator, Adder, classic dual-process state machine, cooked pseudo-random generator, the corresponding Adder test vector, 16 x 8bit RAM, FIFO, etc. source generic RAM
Platform: | Size: 45110 | Author: 蔡孟颖 | Hits:

[Other resource] ram

Description: 本原代码中利用VHDL语言编写了RAM、FIFO、ROM等常用的存储和缓冲部件，完全的代码在ALTERA的FPGA上已经通过仿真测试，保证可用.-primitive code using VHDL prepared RAM, FIFO, ROM, and other commonly used storage and buffer components, complete code in the Altera FPGA simulation test has been passed to ensure that available.
Platform: | Size: 2661 | Author: nick | Hits:

[Other resource] ram

Description: VHDL 编写的RAM例子
Platform: | Size: 2130 | Author: 王攀 | Hits:

[Other resource] ram

Description: fpga中ram的vhdl的经典程序，适用于ALTERA公司器件
Platform: | Size: 1414 | Author: gcy | Hits:

[Other resource] VHDL

Description: 注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化
Platform: | Size: 43546 | Author: 朱明 | Hits:

[Other resource] VHDL-ram_fifo

Description: VHDL的ram和fifo model code 包含众多的厂家
Platform: | Size: 1678507 | Author: SL | Hits:

[Picture Viewer] VGA图像显示

Description:

该项目能将RAM或ROM存储器中储存的十六进制数据显示在VGA显示器上，使用VerilogHDL]语言，在Altera的QuartusII下编译通过。

Platform: | Size: 18145 | Author: submars | Hits:

[Documents] 自动售货机VHDL程序与仿真

Description: library ieee; use ieee.std_logic_arith.all; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity PL_auto1 is port ( clk:in std_logic; --系统时钟 set,get,sel,finish: in std_logic; --设定、买、选择、完成信号 coin0,coin1: in std_logic; --5角硬币、1元硬币 price,quantity :in std_logic_vector(3 downto 0); --价格、数量数据 item0 , act:out std_logic_vector(3 downto 0); --显示、开关信号 y0,y1 :out std_logic_vector(6 downto 0); --钱数、商品数量显示数据 act10,act5 :out std_logic); --1元硬币、5角硬币 end PL_auto1; architecture behav of PL_auto1 is type ram_type is array(3 downto 0)of std_logic_vector(7 downto 0); signal ram :ram_type; --定义RAM signal item: std_logic_vector(1 downto 0); --商品种类 signal coin: std_logic_vector(3 downto 0); --币数计数器 signal pri,qua:std_logic_vector(3 downto 0); --商品单价、数量 signal clk1: std_logic; --控制系统的时钟信号 begin .。。。。。。。。。。。。。
Platform: | Size: 204288 | Author: niuyuanlai@163.com | Hits:

[VHDL-FPGA-Verilog] fifo的vhdl原代码

Description: 本文为verilog的源代码-In this paper, the source code for Verilog
Platform: | Size: 22528 | Author: 艾霞 | Hits:

[VHDL-FPGA-Verilog] sdram_vhd_134

Description: Xilinx Sdram控制器VHDL源代码-Sound code of Xilinx Sdram Controller based on VHDL
Platform: | Size: 54272 | Author: 刘汉忠 | Hits:

[VHDL-FPGA-Verilog] SRAM@DMA实验

Description: ALTERA NIOS处理器实验，QUARTUS下用VHDL编译成处理器，然后NIOS　SHELL下C 语言运行。实验SRAM和DMA调度-Altera NIOS processor experiments QUARTUS using VHDL compiler into processor, then NIOS SHELL C language runtime. Experimental SRAM and DMA Scheduling
Platform: | Size: 33792 | Author: xf | Hits:

[VHDL-FPGA-Verilog] 44vhdl

Description: 44个vhdl实例注1：含有不可综合语句，请自行修改注2：一些PLD只允许I/O口对外三态，不支持内部三态，使用时要注意注3: 设计RAM的最好方法是利用器件厂家提供的软件自动生成RAM元件，并在VHDL程序中例化-44 VHDL examples Note 1 : Includes an integrated statement, the initiative to revise Note 2 : Some PLD only allows I/O external three states, do not support the internal three-state, the use of attention to Note 3 : Design RAM is the best way to use devices provide manufacturers with the software automatically generating RAM components, and the VHDL process cases of
Platform: | Size: 44032 | Author: 土木文田 | Hits:

[Other] VHDLProgrammingbyExample4thEd

Description: 开发硬件的朋友们注意了，这是最新的VHDL编程书籍。里面有大量实用技巧及程序。-hardware attention to the friends, which is the latest VHDL programming books. There are a lot of practical skills and procedures.
Platform: | Size: 1784832 | Author: 孙刚 | Hits:

[VHDL-FPGA-Verilog] blockram

Description: 本人正在学习vhdl语言，买了套开发板，这些是配套光盘里的内容，非常难得，网上找不到的-I was learning VHDL language, bought a set of development boards, which are compatible CD-ROM's content, and very rare. not online! !
Platform: | Size: 21504 | Author: 孙强 | Hits:

[VHDL-FPGA-Verilog] EvsStore

Description: 用VHDL编写的由FPGA控制SDRAM的存储控制程序-VHDL prepared by the FPGA control SDRAM memory control procedures
Platform: | Size: 1024 | Author: | Hits:

[SCM] P.H.Y_programer

Description: 单片机的程序集.大家可以参考一下.我想做一个更好的程序集及电路板.大约在10月份完成.请有兴趣的关注一下.当然我还要做一个通信的vhdl的仿真.-SCM suite. We can take a look. I would like to do a better procedures for collecting and circuit boards. About October completion. those interested in the look. of course, I still have to do a communications VHDL simulation.
Platform: | Size: 28672 | Author: 潘应云 | Hits:

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

Description: sdram_vhdl_lattice，程序已经调通过了，欢迎使用，多多交流哈-sdram_vhdl_lattice, procedures have been transferred through the use of welcome, many exchanges Kazakhstan
Platform: | Size: 181248 | Author: 蒋谦 | Hits:

[VHDL-FPGA-Verilog] my_ramlib_06

Description: 包括各种类型存储器的VHDL描述，如FIFO，双口RAM等 -including various types of memory VHDL description, such as FIFO, Dual Port RAM, etc.
Platform: | Size: 615424 | Author: ruan | Hits:

[SCM] PinYin_InputMethod_C51

Description: 用C51实现的拼音输入法,这是改写的网友 embuffalo、独步上载在www.21ic.com自由发布区的由张凯原作的51上的拼音输入法程序。原作使用了一个二维数组用以查表，我认为这样比较的浪费空间，而且每个字表的索引地址要手工输入，效率不高。所以我用结构体将其改写了一下。就是大家现在看到的这个。因为代码比较的大，共有6,000多汉字，这样就得要12,000 byte来存放GB内码，所以也是没办法的 :-( 编译结果约为3000h,因为大部分是索引表，代码优化几乎无效。在Keil C里仿真芯片选用的是华邦的W77E58，它有32k ROM, 256B on-chip RAM, 1K on-chip SRAM (用DPTR1指针寻址,相当于有1K的片上xdata)。条件有限，没有上片试验，仿真而已。打算将其移植到AVR上，但CodeAVRC与IAR EC++在结构体、指针的定义使用上似乎与C51不太一样，现在还未搞定。还希望在这方面有经验的网友能给予指导。-C51 with the Pinyin input method, which is rewritten netizens embuffalo. Unrivaled www.21ic.com available in the free publication of the original work by Kai-51 on the Pinyin input method procedures . Appreciate the use of a two-dimensional array for the look-up table, I think this is a waste of space. Each of the characters but the index table to manually input address, efficiency is not high. I use the structure to rewrite a bit. We see now is this. Because the code comparison, a total of 6, more than 000 Chinese characters, this must be 12, byte to store 000 GB code, is not the way to compile results :-( about 3000h. because most of the index table. Code Optimization almost ineffective. Keil in the C simulation uses the chip in W77E58 Winbond, It has 32 k ROM 256B on-chip RAM, 1K on-chi
Platform: | Size: 14336 | Author: Jawen | Hits:

[VHDL-FPGA-Verilog] 用vhdl写实用96例子

Description: 用vhdl写实用96例子, 有RAM，PID 等(Using VHDL to write practical examples of 96, there are RAM, PID and so on)
Platform: | Size: 17153024 | Author: 朱朱8 | Hits:

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[Other resource] 一些VHDL源代码

[Other resource] ram

[Other resource] ram

[Other resource] ram

[Other resource] VHDL

[Other resource] VHDL-ram_fifo

[Picture Viewer] VGA图像显示

[Documents] 自动售货机VHDL程序与仿真

[VHDL-FPGA-Verilog] fifo的vhdl原代码

[VHDL-FPGA-Verilog] sdram_vhd_134

[VHDL-FPGA-Verilog] SRAM@DMA实验

[VHDL-FPGA-Verilog] 44vhdl

[Other] VHDLProgrammingbyExample4thEd

[VHDL-FPGA-Verilog] blockram

[VHDL-FPGA-Verilog] EvsStore

[SCM] P.H.Y_programer

[VHDL-FPGA-Verilog] sdram_vhdl_lattice

[VHDL-FPGA-Verilog] my_ramlib_06

[SCM] PinYin_InputMethod_C51

[VHDL-FPGA-Verilog] 用vhdl写实用96例子

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